Switching Theory and Logic Design
Assignment - 1
SUBJECT CODE-- ETEC 202
BATCH- MAE 789
SUBMISSION DATE - 26 FEBRUARY 2020
1. Design 4 bit Serial Adder circuit.
2. Design a Parity Generator Circuit.
3. Discuss the structure, properties and application of the following:-
(a) ALU (b) PAL (c) PLA
(a) ALU (b) PAL (c) PLA
4. Design a Carry Save Adder Circuit.
5. Design 4 bit Magnitude Comparator Circuit.
6. Design BCD to 7 Segment decoder for displaying 7.
7. Compare RAM and ROM along with their types.
8. Obtain the minimal expression using Quine- McCluskey method-
F(A,B,C,D) = Sigma m(1,5,6,12,13,14)+d(2,4)
7. Compare RAM and ROM along with their types.
8. Obtain the minimal expression using Quine- McCluskey method-
F(A,B,C,D) = Sigma m(1,5,6,12,13,14)+d(2,4)
