Switching Theory and Logic Design - ETEC- 202

Switching Theory and Logic Design

Assignment - 1

SUBJECT CODE-- ETEC 202

BATCH- MAE 789

SUBMISSION DATE - 26 FEBRUARY 2020

1. Design 4 bit Serial Adder circuit.

2. Design a Parity Generator Circuit.

3. Discuss the structure, properties and application of the following:-
(a) ALU              (b) PAL                (c) PLA

4. Design a Carry Save Adder Circuit.

5. Design 4 bit Magnitude Comparator Circuit.

6. Design BCD to 7 Segment decoder for displaying 7.

7. Compare RAM and ROM along with their types.

8. Obtain the minimal expression using Quine- McCluskey method-
      F(A,B,C,D) =  Sigma m(1,5,6,12,13,14)+d(2,4)
   

Submit the Assignment on vaibhavnijhawan@mait.ac.in by due date.

Assignment -Microprocessor and Micro controller 2019

Assignment 

Microprocessor and Micro controller

SUBJECT CODE-- ETEE 310                                                                         Date -- 12 Feb 2019

BATCH- EE-456, EE-789

SUBMISSION DATE - 21 Feb 2019

1. Design a microprocessor 8086 system having two 4K X 8 EPROM and four 8K X 8 RAM. Avoid any foldback addresses.

2. What do you mean by segment over ride prefix? Write the instruction format for

MOV DS: 2345 [BP], DX.

3. Differentiate memory mapped I/O and I/O mapped I/O?

4. What are the Logical and Physical addresses? How the physical addresses are generated ?

5. Interface Stepper Motor to 8086 using 8255 and write Assembly Language Program

to rotate Stepper Motor in Clockwise direction and in full stepping. Assume that

8255 is interfaced with 8086 in memory mapped IO.

6. What do you understand by assembler directives in 8086?

7. Write an ALP to produce a delay of 1 second. Consider the 8085 clocked at 5 Mhz.

8. Explain the following instructions (8086):-

(a) SCASB         (b) LEA      (c) AAA       (d) CBW      (e) TEST      (f) STOS